HBM3E 36GB 12-Hi Stacks — Highest-Capacity HBM3E Stack

Schematic illustration of an HBM stacked package: DRAM dies stacked with through-silicon vias on a silicon interposer beside a logic die — Schematic of an HBM stack: DRAM dies stacked vertically with through-silicon vias, placed beside a logic die on a silicon interposer. Each stock line below is a separate physical lot of this stack, supplied by exact part number.

36 GB is the ceiling of the HBM3E generation in practice: twelve 24Gb layers in a 12-high stack, on the same 1024-bit device interface and the same JESD238 lineage as the 16 GB and 24 GB parts before it.

It exists because capacity per stack, not bandwidth, became the constraint: 8-high HBM3E stops at 24 GB, and the next step up on the same package is stack height. Buyers looking at 288 GB class modules (eight stacks of 36 GB) are buying exactly this part.

Where the 24 GB 8-high stack is documented against the H200, the 36 GB 12-high stack is the current-generation part: SK hynix announced mass production of 12-high HBM3E in 2024, and the 288 GB boards announced since then are consistent with eight 36 GB stacks.

JEDEC specification

Generation	Standard	Stack heights	Capacity per stack	Per-stack bandwidth	Device interface
HBM2	JESD235A (2016-01-12)	2 / 4 / 8-Hi	1-8 GB	256 GB/s (307 GB/s @2.4 Gbps)	1024-bit / 8 ch
HBM2E	JESD235B (2018-12-17)	2 / 4 / 8 / 12-Hi	1-24 GB	307 GB/s	1024-bit / 8 ch
HBM3	JESD238 (2022-01-27)	4 / 8 / 12-Hi	4-64 GB	819 GB/s @6.4 Gb/s	1024-bit / 16 ch
HBM3E	JESD238 enhancement	8-Hi / 12-Hi	24 GB (8-Hi) / 36 GB (12-Hi)	>1.2 TB/s	1024-bit

Values are the published JEDEC standard limits for each generation (JESD235A / JESD235B / JESD238). The highlighted row is the generation of this page. Stack height, not the interface, is what changes capacity: the device interface stays 1024-bit on HBM2, HBM2E and HBM3, and each stack runs 8 or 16 independent channels.

Where this stack size is used

12-high versus 8-high HBM3E: Identical interface and channel structure; 36 GB against 24 GB per stack. This is the same stack-height lever JEDEC has used since HBM2, applied to the densest current die. Source: JEDEC HBM3 JESD238 (2022)
288 GB class accelerators: Eight 36 GB stacks = 288 GB on a 8192-bit class bus. Vendor announcements for the current 288 GB HBM3E parts are consistent with that configuration; treat the stack count as an arithmetic consequence of published capacity and bus width rather than a vendor-published figure. Source: TechPowerUp B200 SXM6 (180GB / 8192-bit)

Stock lines in this family

Part number	Brand	CIP to your address	Stock line
MTG5B18G16120A00QH-92:A	Micron	US$ 1,995	VRAM-HBM3e-MIC-25
H5UGVHAF03X043R	SK hynix	US$ 1,995	VRAM-HBM3e-HYN-21
KHBBC4B03C-MC1KT00	Samsung	US$ 1,995	VRAM-HBM3e-SAM-19

Prices are listed per piece CIP delivered to your address and are set against publicly published competitor asks, checked 12 Nov; the basis for each figure is recorded on the individual stock line. Stock is physical and held in Shenzhen — inspection before shipment is available on request. We supply against your order quantity: send the quantity you need and the price break, condition grade (new / pulled / refurbished) and lead time are confirmed in writing.

Frequently asked about HBM3E 36GB 12-Hi

What is the total capacity of a single HBM3E 36GB stack?

A single HBM3E 36GB stack consists of 12 dies, each with a 24Gb capacity, resulting in a total of 36GB per stack. This configuration represents the current top capacity point for HBM3E modules under the JEDEC standard.

How many HBM3E stacks are required for a 288GB GPU memory configuration?

A 288GB memory configuration typically utilizes eight HBM3E stacks, each providing 36GB of capacity. This arrangement is consistent with documented high-end GPU architectures that aggregate multiple stacks to reach this total memory size.

Is the HBM3E 36GB stack compliant with the JEDEC standard?

Yes, the HBM3E 36GB stack adheres to the JEDEC HBM3E standard specifications. It features a 12-high stack configuration with 24Gb dies, which is the maximum density currently defined for this generation of high-bandwidth memory.

Sources

Every figure on this page is traceable: statements taken directly from official sources, and derived numbers (stack counts from published bus widths, capacity per stack from published totals) are marked as derived in the text. Facts checked 30 Sep.

Look up a part number in the cross-reference or ask us for a quote.